Maximizing memory bandwidth, i.e., the rate at which data can be written or read, is an important factor in memory device performance. Memory bandwidth has been increased to some extent by prefetching data so that the data will be available when it is called for by a received memory command. As memory bandwidth demands have increased, the amount of data that is prefetched for each read or applied to the memory device for each write has continued to increase as well. However, simply continuing to increase the amount of date prefetched results in a great deal of data being prefetched from a single location in memory. Taken to its extremes, data from an entire page of memory will be prefetched. Unfortunately, such a large amount of data from a single location is often not desired. It would be desirable to be able to prefetch smaller amounts of data from different banks at the same time. Yet the internal structure of memory devices, such as dynamic random access memory (“DRAM”) devices precludes them from operating in a manner that provides more flexibility in data prefetch locations.
A portion of a typical DRAM device 10 is shown in FIG. 1. The DRAM device 10 includes an address buffer 14 that receives bank, row and column addresses through an external address bus 18. A bi-direction data buffer 20 receives write data through an external data bus 24, and outputs read data to the data bus 24. Finally, a command decoder 30 receives and decodes memory commands, such as read command and write commands, through an external command bus 34. The DRAM device 10 also includes other circuitry as will be appreciated by one skilled in the art, but, in the interest of brevity, such circuitry has been omitted from FIG. 1.
The DRAM device 10 includes first and second memory array banks 40, 44, although additional banks (not shown) may be included. Each of the banks 40, 44 contains a large number of memory cells arranged in rows and columns. In response to read or write command signals received from the command decoder 30 through an internal command bus 50, data are coupled through an internal global data bus 52 to or from one of the banks 40, 44. The particular row to which the data are written or from which the data are read is designated by a row address received from the address buffer 14 through an internal global address bus 54. As is well known in the art, once a row of memory cells has been opened, the memory cells in the open row can be readily accessed. As a result, data in an open row can be easily prefetched. It requires substantially more time to open a different row in the same or a different one of the banks 40, 44. A particular column in an open row from which data are read or to which data are written is identified by a column address received from the address buffer 14.
It can be seen from FIG. 1 that the DRAM device 10 has a single internal command bus 50, a single internal data bus 52 and a single internal address bus 54. Although the internal data bus 52 may be divided into separate read data and write data paths, the data bus 52 can serve only one of the banks 40, 44 at a time. Similarly, the single internal command bus 50 and the single internal address bus 54 cannot simultaneously address and provide commands to both of the banks 40, 44. As a result, the DRAM device 10 is incapable of concurrently prefetching data from different rows of memory cells in the same or in different banks 40, 44.
There is therefore a need for a method and system for concurrently accessing different rows of memory cells in the same or in different banks so that prefetches of smaller block of data in different locations can occur while still providing a high memory bandwidth.